• Develop testbenches using System Verilog and UVM for functional and power aware RTL
• Develop UVM component like agents (active and passive), scoreboards and environment etc., Develop assertions, functional coverage.
• Drive closure of verification metrics to cover verification space. Work with the team to identify and close gaps in functional, power aware and Gate level timing simulation.
• Provide regression setup, debug of RTL and gate level netlist
• Review industry standard spec and augment test plan to improve quality of verification
• Participate in post silicon bring up, validation and compliance testing and debug
• Work collaboratively with cross-functional teams like product Architect,  Designers, project leads.

Who we are looking for

• Proven expertise with UVM and/or System Verilog based verification
• Excellent understanding of ASIC verification methodologies and proven experience of verification
• Experience working with source control tools, bug management tools and release management tools such as Jenkins, Git, and Jira.
• Strong written and verbal communication skills and ability to work independently.
• Bachelors in Electrical Engineering or equivalent and 6+ years of experience

Please contact Soi Kim Kee for further information via suki.kee@ams-osram.com or +65 () 62402395.