We are looking for a Senior Principal Analog Designer to act as the primary technical interface between R&D and the Foundry Product Line.
The role focuses on enabling external customers to design in our technologies through a reusable analog IP library that supports our customers.
Analog IP Portfolio Ownership
- Manage and maintain the full catalog of analog and mixed signal IPs (ADCs, DACs, amplifiers, oscillators, PLLs, LDOs, PORs, sensors, IO/ESD, memories, etc.)
- Provide complete models, verification data, simulation test benches, documentation, and IP revision/history tracking
- Maintain structured bug tracking and customer notification flows
- Facilitate internal reuse by ensuring IPs are robust, documented, and straightforward to integrate into product designs
Foundry Interface
- Act as the main R&D contact for the Foundry Product Line
- Represent analog and mixed signals design requirements in foundry related discussions
- Interaction With Corporate functions & BL RD
- Collaborate closely with central R&D / technology development teams on PDK, device models, design rules, simulation views, and technology options
IP Strategy & Gap Analysis
- Assess completeness of the IP portfolio and actively contribute to building the roadmap of IP based on customer demands
- Drive make or buy evaluations and proposals for new IP developments based on customer and business needs
- Serve as main interface to and manage 3rd parties providing IPs in a “buy” model
Technical Leadership
- Oversee a small team of IP design engineers developing IP blocks for foundry customers
- Technical guidance and design review / design challenge for IP blocks being designed by other IP design engineers
- Hands-on design of most critical / most challenging IP blocks
- Planning timelines, workload and related capacity
Who we are looking for
- University degree in Electronics or other related technical education
- 12+ years of experience in analog/mixed signal IC design
- Deep expertise in key analog domains (data converters, references, oscillators/PLLs, LDOs, IO/ESD, etc.)
- Strong understanding of CMOS 0.18 µm class technologies and PDK/modeling flows
- Excellent communication skills and experience working with customers and cross functional technical teams
- Experience with IP reuse, release flows, IP-centric development flows and quality management is highly preferred
- Knowledge of English is mandatory, German is an advantage
We offer competitive salaries and additional benefits based on your performance, experience and qualification.
The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group H (https://www.feei.at/aktuelles/mindestloehne-und-gehaelter-eei/). We offer a higher compensation depending on your expertise and skills.
Please contact Hana Krsul for further information via Hana.Krsul@ams-osram.com or +43 664 9665611.