The Senior Principal Mixed-Signal Verification Engineer leads and mentors a distributed team of Mixed Signal Verification Engineers, ensuring technical excellence, consistent methodologies and continuous people development and knowledge sharing across all sites. Manages internal teams and external design house partners, balancing workloads, scaling resources and ensuring predictable execution in environments with fluctuating demand. Acts as the primary interface for R&D leaders, Project Managers, and Technical Leads, driving planning, task sequencing, risk mitigation and resource allocation for all verification activities. Owns and drives the AMS/DMS verification methodology and long term roadmap, ensuring alignment of tools, flows, standards and strategic technology decisions throughout the organization.

• Develops and leads the maintenance of high quality AMS/DMS behavioral models and reusable model libraries (EEnet/UDN), defining modeling standards and ensuring consistency across products
• Runs DMS simulations and correlates them with transistor level Spectre results, performing root cause analysis, refining models, and using analog judgment to distinguish real circuit issues from modeling limitations
• Builds, extends, and maintains DMS verification environments using SystemVerilog and UVM MS, including testbenches, mixed signal assertions, critical scenarios, and coverage. Also designs and maintains the mixed signal regression infrastructure (capacity, debugging, failure analysis)
• Executes verification across PVT variations and interprets corner results effectively
• Automates simulation execution, data analysis, correlation, and reporting using Python to improve efficiency and traceability
• Analyzes schematics, predicts circuit behavior, and solves complex analog or mixed signal problems independently
• Defines AMS/DMS coverage metrics and formal sign off criteria, including coverage closure, transistor level correlation, interface validation, and specification compliance
• Collaborates effectively with Digital Design, SoC Verification, Firmware, and Architecture teams to ensure proper functional integration and interface consistency

Who we are looking for

• University degree in Electronics or other related technical education
• 10+ years of experience in analog or mixed-signal circuit design or analog verification with direct involvement in projects through tape-out or product completion
• Deep analog circuit expertise applied to DMS verification using SystemVerilog EEnet/UDN, accurately modeling real world effects such as loading, impedance interactions, noise and non idealities
• Strong expertise in analog circuits (op amps, references, ADC/DAC architectures, low noise front ends, sensor interfaces, bio signal circuits)
• Deep knowledge of analog performance metrics (offset, drift, noise, CMRR, PSRR, THD, SFDR, ENOB, bandwidth, settling time, INL/DNL, stability)
• Strong technical communication skills with the ability to clearly explain complex analog concepts to cross-functional teams
• knowledge of English is mandatory, German / Italian is an advantage depending on the office location

For Austria: We offer competitive salaries and additional benefits based on your performance, experience and qualification.
The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group H (https://www.feei.at/aktuelles/mindestloehne-und-gehaelter-eei/). We offer a higher compensation depending on your expertise and skills.

Please contact Hana Krsul for further information via Hana.Krsul@ams-osram.com or +43 664 9665611.