- Perform digital design layout, place & route for complex integrated circuits
- Execute Clock Tree Synthesis (CTS) and timing-driven layout
- Define and manage SDC timing constraints for synthesis and place & route flow
- Conduct parasitic extraction and signal integrity analysis
- Run Static Timing Analysis (STA) and manage ECO flows
- Ensure layout finishing including LVS, DRC, antenna checks
- Help to debug designs at both pre- and post-silicon
- Collaborate with cross-functional teams to deliver optimized backend solutions
Who we are looking for
- Successfully completed studies in Electrical Engineering, Electronics, Computer Science or similar field
- Several years (10+) of experience in digital IC design
- Strong proficiency in digital backend design tools and flows (Cadence flow)
- Hands-on experience with 22nm and above process technologies
- Solid understanding of timing closure, signal integrity, and physical verification
- Ability to work independently and in team environments
- Excellent problem-solving and communication skills
- Strong communication skills in English
Please contact Julia Zajac for further information via JULIA.ZAJAC@AMS-OSRAM.COM or +48 (61) 8809988.